DS495 Datasheet, PDF (1/12 Pages) Xilinx, Inc – PCI Arbiter

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PCI Arbiter (v1.00a)
DS495 April 8, 2009
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Product Specification
Introduction
The PCI Arbiter provides arbitration for two to eight
PCI master agents. Parametric selection determines the
number of masters competing for PCI bus control.
Arbitration follows a rotating scheme to provide fair
access to the PCI bus for all master agents. Bus parking
occurs when no master requests PCI control. The last
active master – the most recent master to request,
control, and relinquish the bus – is designated as the
park master agent. When multiple masters request
control of the PCI bus, the highest priority master
request will be granted for a minimum of two PCI clock
cycles, then the grant will be removed. This allows the
granted agent to control the bus for the duration of its
latency timer. Upon expiration of its latency timer, this
agent must relinquish the bus and allow the PCI
Arbiter to grant control to the next highest priority
requesting master agent. Transitions between distinct
grant signal assertions are always separated by one PCI
clock cycle when all grant signals are deasserted.
Formerly known as the OPB_PCI_Arbiter, this new
core does not provide an option for the inclusion of an
OPB interface or programmable registers. Loss of the
marginal utility of an OPB interface and the program
registers is compensated by a more robust
implementation with more clearly defined operations.
The PCI_Arbiter follows guidelines defined in the PCI
Local Bus Specification, Version 3.0, February 3, 2004.
The PCI_Arbiter is designed for operation in 33 and 66
MHz PCI systems.
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Spartan®-3, Spartan-3E,
Virtex®-4 and Virtex-5
Version of core
pci_arbiter
v1.00a
Resources Used
Min
Max
LUTs
FFs
See Table 5 and Table 6
Block RAMs
Provided with Core
Documentation
Product Specification
Design File Formats VHDL
Constraints File
N/A
Verification
N/A
Instantiation
Template
N/A
Reference Designs
& application notes
N/A
Additional Items
Design Tool Requirements
Xilinx®
Implementation
Tools
ISE® v11.1 or later
Verification
Mentor Graphics ModelSim v6.4b
and above
Simulation
Mentor Graphics ModelSim v6.4b
and above
Synthesis
XST 11.1 or later
Support
Provided by Xilinx, Inc.
© 2006-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trade-
marks are the property of their respective owners.
DS495 April 8, 2009
www.xilinx.com
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Product Specification