DS495 Datasheet, PDF (2/12 Pages) Xilinx, Inc – PCI Arbiter

PCI Arbiter (v1.00a)
Features
• Variable number of PCI masters set by a parameter
• Rotating arbitration
• Bus parking
• Grant deasserts to invoke the granted master latency timer for cases of multiple requests
• Minimum two clock cycle grant assertion
• Grants deasserts one cycle between grant transitions
• The last active master is the default for bus parking
Functional Description
The top-level block diagram of the PCI Arbiter is shown in Figure 1.
Figure Top x-ref 1
PCI_Rst_n
PCI_Clk
PCI_Req_n
PCI_Frame_n
PCI_Irdy_n
PCI
Sync
Register
Last Active
Master Register
Arbiter
Bus Requests
Park
Mux
PCI State
Machine
Figure 1: PCI Arbiter Block Diagram
PCI
Grant
Register
PCI_Gnt_n
pci_arbiter_block_diagram
PCI_Arbiter I/O Signals
The I/O signals for the PCI_Arbiter are listed in Table 1 and are shown in Figure 1, the PCI_Arbiter
block diagram.
Table 1: PCI_Arbitier I/O Signals
Port
Signal Name
Interface I/O
Description
PCI Interface
P1 PCI_Clk
PCI
I PCI Clock
P2 PCI_Rst_n
PCI
I PCI Reset, active low
P3 PCI_Req_n[0: C_NUM_PCI_MSTRS - 1]
PCI
I PCI Request, active low
P4 PCI_Gnt_n[0: C_NUM_PCI_MSTRS - 1]
PCI
O PCI Grant, active low
P5 PCI_Frame_n
PCI
I PCI Frame, active low
P6 PCI_Irdy_n
PCI
I PCI Ready, active low
2
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DS495 April 8, 2009
Product Specification