DS495 Datasheet, PDF (4/12 Pages) Xilinx, Inc – PCI Arbiter

PCI Arbiter (v1.00a)
Rotating Arbitration Scheme
The rotating arbitration scheme shifts the priority level for every PCI master following each bus
arbitration cycle. Immediately after reset, PCI master zero has the highest priority level, level zero.
From the highest priority, the priority level decreases as the PCI master number increases. Each
arbitration cycle causes all of the priority levels to shift. The PCI master agent with the highest priority,
zero, receives the lowest priority, C_NUM_PCI_MSTRS-1, while the remaining PCI master agents
receive higher level priorities. Over time, this provides equal bus access for all PCI master agents.
Table 4 illustrates the rotating arbitration scheme with eight masters, C_NUM_PCI_MSTRS = 8. Each
column denotes the appropriate priority level for the PCI master in a given row and time is increasing
from left to right. These priorities shift in this nature regardless of which master agent wins access to
the bus. At any point when multiple masters agents compete for bus access, the competing master with
the highest priority shall be granted access and all masters will receive new priority levels. Any agent
failing to obtain bus access will receive progressively higher priority levels for each arbitration cycle
and eventually obtain bus access.
Table 4: Rotating Arbitration Scheme for 8 PCI Master Agents (C_NUM_PCI_MSTRS = 8).
0
0
7
6
5
4
3
2
1
0
7
1
1
0
7
6
5
4
3
2
1
0
2
2
1
0
7
6
5
4
3
2
1
3
3
2
1
0
7
6
5
4
3
2
4
4
3
2
1
0
7
6
5
4
3
5
5
4
3
2
1
0
7
6
5
4
6
6
5
4
3
2
1
0
7
6
5
7
7
6
5
4
3
2
1
0
7
6
4
www.xilinx.com
DS495 April 8, 2009
Product Specification