DS495 Datasheet, PDF(7/12 Page) Xilinx, Inc

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DS495 Datasheet, PDF (7/12 Pages) Xilinx, Inc – PCI Arbiter

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PCI Arbiter (v1.00a)

The PCI Specification allows a requesting PCI master to assert PCI_Frame_n in the same clock cycle

that the PCI_Arbiter is removing PCI_Gnt_n. This is defined as a valid response by the requesting

master and the PCI Arbiter must accommodate this transaction. This requesting master would then be

recorded as the last active master. Figure 4 illustrates this case by the deassertion of PCI_Gnt_n(3) just

as PCI_Frame_n is asserted. The PCI_Arbiter reasserts PCI_Gnt_n(3) to acknowledge and allow the bus

transaction, then records master agent number three as the last active master as seen in the park mode

when the PCI bus goes idle.

Figure Top x-ref 4

pci_clk

pci_rst_n

pci_req_n(0)

pci_req_n(1)

pci_req_n(2)

pci_req_n(3)

pci_req_n(4)

pci_req_n(5)

pci_frame

pci_irdy_n

pci_gnt_n(0)

pci_gnt_n(1)

pci_gnt_n(2)

pci_gnt_n(3)

pci_gnt_n(4)

pci_gnt_n(5)

X495_04_101106

Figure 4: PCI_Frame_n Response in the Clock Cycle That PCI_Gnt_n is Removed

Figure 5 shows that the last active master, while in park mode, may request and be granted control of

the PCI bus. In this case, the PCI_Arbiter must recognize and grant the request. This PCI master will

retain its status as the last active master. Figure 5 starts with master agent number one as the park

master but transitions the park master to agent number two following the request and transaction of

master agent number two. The last transaction illustrates the park master requesting and obtaining PCI

bus access.

Figure Top x-ref 5