DS495 Datasheet, PDF (12/12 Pages) Xilinx, Inc – PCI Arbiter

PCI Arbiter (v1.00a)
The PCI_Arbiter resource utilization measured with the Virtex-5 FPGA as the target device are detailed
in Table 6.
Table 6: Performance and Resource Utilization Benchmarks on Virtex-5 FPGA (xc5vlx50-2-ff1153)
Parameter Values
Sr. No.
C_NUM_PCI_MSTRS
Device Resources
Slice Flip - Flops
LUTs
f_MAX(MHz)
1
2
14
53
177.49
2
3
24
65
168.92
3
4
30
72
159.67
4
5
46
99
120.24
5
6
54
104
133.62
6
7
62
123
114.13
7
8
70
122
121.07
Reference Documents
The following document contains reference information important to understanding the PCI_Arbiter:
• PCI Local Bus Specification, Revision 3.0, February 03, 2004.
Revision History
Date
11/12/04
7/14/06
10/16/06
04/24/09
Version
1.0
1.1
1.2
1.3
Revision
Initial Xilinx release
Updated for Virtex-5 support
Converted to new DS template; images updated to graphic standards
Updated tool support and legal information.
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DS495 April 8, 2009
Product Specification