XC4013E Datasheet, PDF (61/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

R
XC4000E and XC4000X Series Field Programmable Gate Arrays
CCLK
INIT
DOUT
RDY/BUSY
BYTE
0
BYTE
1
BYTE 0 OUT
BYTE 1 OUT
0
1
2
3
4
5
6
7
0
1
X6096
Description
Symbol
Min
Max
Units
INIT (High) setup time
T_IC
5
µs
CCLK
D0 - D7 setup time
D0 - D7 hold time
CCLK High time
T_DC
60
T_CD
0
T_CCH
50
ns
ns
6
ns
CCLK Low time
T_CCL
60
ns
CCLK Frequency
F_CC
8
MHz
Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
Figure 57: Synchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
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