XC4013E Datasheet, PDF (49/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Length Count Match
CCLK Period
CCLK
F
DONE
XC2000
I/O
Global Reset
F
XC3000
DONE
I/O
Global Reset
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
F
DONE
C1
C2
C3
C4
XC4000E/X
I/O
CCLK_NOSYNC
C2
C3
C4
GSR Active
6
C2
C3
C4
DONE IN
F
DONE
XC4000E/X
CCLK_SYNC
C1, C2 or C3
I/O
Di
Di+1
GSR Active
Di Di+1
F
XC4000E/X
UCLK_NOSYNC
DONE
C1
I/O
U2
U3
U4
U2
U3
U4
GSR Active
XC4000E/X
UCLK_SYNC
DONE
C1
I/O
U2
U3
U4
DONE IN
F
U2
Di Di+1
Di+2
GSR Active
Synchronization
Uncertainty
Figure 47: Start-up Timing
Di Di+1
Di+2
UCLK Period
X9024
May 14, 1999 (Version 1.6)
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