XC4013E Datasheet, PDF (59/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

R
XC4000E and XC4000X Series Field Programmable Gate Arrays
A0-A17
(output)
D0-D7
RCLK
(output)
CCLK
(output)
DOUT
(output)
Address for Byte n
Byte
2 T_DRC
7 CCLKs
Address for Byte n + 1
1 T_RAC
3 T_RCD
CCLK
D6
Byte n - 1
D7
X6078
Description
Symbol
Min
Max
Units
6
Delay to Address valid
1
T_RAC
0
200
ns
RCLK
Data setup time
2
T_DRC
60
ns
Data hold time
3
T_RCD
0
ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 55: Master Parallel Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
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