XC4013E Datasheet, PDF (45/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 20: XC4000E Program Data
Device
Max Logic Gates
CLBs
(Row x Col.)
IOBs
Flip-Flops
Bits per Frame
Frames
Program Data
PROM Size
(bits)
XC4003E
3,000
100
(10 x 10)
80
360
126
428
53,936
53,984
XC4005E
5,000
196
(14 x 14)
112
616
166
572
94,960
95,008
XC4006E
6,000
256
(16 x 16)
128
768
186
644
119,792
119,840
XC4008E
8,000
324
(18 x 18)
144
936
206
716
147,504
147,552
XC4010E
10,000
400
(20 x 20)
160
1,120
226
788
178,096
178,144
XC4013E
13,000
576
(24 x 24)
192
1,536
266
932
247,920
247,968
XC4020E
20,000
784
(28 x 28)
224
2,016
306
1,076
329,264
329,312
XC4025E
25,000
1,024
(32 x 32)
256
2,560
346
1,220
422,128
422,176
Notes:
1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading ones at the beginning of the header.
Table 21: XC4000EX/XL Program Data
Device
Max Logic
XC4002XL XC4005 XC4010 XC4013 XC4020 XC4028 XC4036 XC4044 XC4052 XC4062 XC4085
2,000 5,000 10,000 13,000 20,000 28,000 36,000 44,000 52,000 62,000 85,000
6
Gates
CLBs
(Row x
Column)
64
196
400
576
784 1,024 1,296 1,600
1,936
2,304
3,136
(8 x 8) (14 x 14) (20 x 20) (24 x 24) (28 x 28) (32 x 32) (36 x 36) (40 x 40) (44 x 44) (48 x 48) (56 x 56)
IOBs
64
112
160
192
224
256
288
320
352
384
448
Flip-Flops
256
616 1,120 1,536 2,016 2,560 3,168 3,840
4,576
5,376
7,168
Bits per
Frame
133
205
277
325
373
421
469
517
565
613
709
Frames
459
741 1,023 1,211 1,399 1,587 1,775 1,963
2,151
2,339
2,715
Program Data 61,052 151,910 283,376 393,580 521,832 668,124 832,480 1,014,876 1,215,320 1,433,804 1,924,940
PROM Size
(bits)
61,104 151,960 283,424 393,632 521,880 668,172 832,528 1,014,924 1,215,368 1,433,852 1,924,992
Notes:
1. Bits per frame = (13 x number of rows) + 9 for the top + 17 for the bottom + 8 + 1 start bit + 4 error check bits.
Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4.
Program data = (bits per frame x number of frames) + 5 postamble bits.
PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte.
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end
of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading “ones” at the beginning of the header.
Cyclic Redundancy Check (CRC) for
Configuration and Readback
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans-
mitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and com-
pares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 19. If a frame data
error is detected during the loading of the FPGA, the con-
figuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in Figure 45. The checksum consists of the 11 most signif-
icant bits of the 16-bit code. A change in the checksum indi-
cates a change in the Readback bitstream. A comparison
to a previous checksum is meaningful only if the readback
data is independent of the current device state. CLB out-
puts should not be included (Read Capture option not
May 14, 1999 (Version 1.6)
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