XC4013E Datasheet, PDF (13/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

R
XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C1 • • • C4
WE
D1
D0
EC
G1 • • • G4
Enable
DIN
WRITE
16-LATCH
DECODER
ARRAY
MUX
G'
4
1 of 16
4
READ ADDRESS
Enable
DIN
F1 • • • F4
WRITE
16-LATCH
DECODER
ARRAY
MUX
F'
4
1 of 16
4
X6746
READ ADDRESS
6
Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM
4
C1 • • • C4
WE
D1/A4
D0
EC
G1 • • • G4
F1 • • • F4
Enable
DIN
WRITE
16-LATCH
DECODER
ARRAY
MUX
4
1 of 16
4
READ ADDRESS
Enable
DIN
WRITE
16-LATCH
DECODER
ARRAY
MUX
4
1 of 16
4
READ ADDRESS
Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)
May 14, 1999 (Version 1.6)
G'
H'
F'
X6749
6-17