XC4013E Datasheet, PDF (43/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
is passed through and is captured by each FPGA when it tiated and most boundary scan instructions cannot be
recognizes the 0010 preamble. Following the length-count used.
data, each FPGA outputs a High on DOUT until it has
received its required number of data frames.
The user has some control over the relative timing of these
events and can, therefore, make sure that they occur at the
After an FPGA has received its configuration data, it proper time and the finish point F is reached. Timing is con-
passes on any additional frame start bits and configuration trolled using options in the bitstream generation software.
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value
XC3000 Master with an XC4000 Series Slave
of the 24-bit length count, the FPGAs begin the start-up _{Some designers want to use an inexpensive lead device in}
sequence and become operational together. FPGA I/O are _{peripheral mode and have the more precious I/O pins of the}
normally released two CCLK cycles after the last configura- _{XC4000 Series devices all available for user I/O. Figure 44}
tion bit is received. Figure 47 on page 53 shows the _{provides a solution for that case.}
start-up timing for an XC4000 Series device.
This solution requires one CLB, one IOB and pin, and an
The daisy-chained bitstream is not simply a concatenation _{internal oscillator with a frequency of up to 5 MHz as a}
of the individual bitstreams. The PROM file formatter must _{clock source. The XC3000 master device must be config-}
be used to combine the bitstreams for a daisy-chained con- _{ured with late Internal Reset, which is the default option.}
figuration.
One CLB and one IOB in the lead XC3000-family device
Multi-Family Daisy Chain
are used to generate the additional CCLK pulse required by
the XC4000 Series devices. When the lead device removes
All Xilinx FPGAs of the XC2000, XC3000, and XC4000 _{the internal RESET signal, the 2-bit shift register responds}
Series use a compatible bitstream format and can, there- _{to its clock input and generates an active Low output signal}
fore, be connected in a daisy chain in an arbitrary _{for the duration of the subsequent clock period. An external}
sequence. There is, however, one limitation. The lead _{connection between this output and CCLK thus creates the}
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device must belong to the highest family in the chain. If the _{extra CCLK pulse.}
chain contains XC4000 Series devices, the master nor-
mally cannot be an XC2000 or XC3000 device.
The reason for this rule is shown in Figure 47 on page 53.
Since all devices in the chain store the same length count
value and generate or receive one common sequence of
CCLK pulses, they all recognize length-count match on the
same CCLK edge, as indicated on the left edge of
Figure 47. The master device then generates additional
CCLK pulses until it reaches its finish point F. The different
families generate or require different numbers of additional
CCLK pulses until they reach F. Not reaching F means that
the device does not really finish its configuration, although
DONE may have gone High, the outputs became active,
and the internal reset was released. For the XC4000 Series
device, not reaching F means that readback cannot be ini-
Reset
00
10
11
01
01
.. ^etc ..
Active Low Output
Active High Output
OE/T
Output
Connected
to CCLK
X5223
Figure 44: CCLK Generation for XC3000 Master
Driving an XC4000 Series Slave
May 14, 1999 (Version 1.6)
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