XC4013E Datasheet, PDF (1/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

0
R
XC4000E and XC4000X Series Field
Programmable Gate Arrays
May 14, 1999 (Version 1.6)
0 0* Product Specification
XC4000E and XC4000X Series
Low-Voltage Versions Available
Features
• Low-Voltage Devices Function at 3.0 - 3.6 Volts
Note: Information in this data sheet covers the XC4000E,
XC4000EX, and XC4000XL families. A separate data sheet
• XC4000XL: High Performance Low-Voltage Versions of
XC4000EX devices
covers the XC4000XLA and XC4000XV families. Electrical
Specifications and package/pin information are covered in
Additional XC4000X Series Features
separate sections for each family to make the information _{• Highest Performance — 3.3 V XC4000XL}
easier to access, review, and print. For access to these sec-
tions, see the Xilinx WEBLINX web site at
• Highest Capacity — Over 180,000 Usable Gates
• 5 V tolerant I/Os on XC4000XL
http://www.xilinx.com/partinfo/databook.htm#xc4000.
• 0.35 µm SRAM process for XC4000XL
• Additional Routing Over XC4000E
• System featured Field-Programmable Gate Arrays
- almost twice the routing capacity for high-density
- Select-RAM^TM memory: on-chip ultra-fast RAM with
designs
- synchronous write option
• Buffered Interconnect for Maximum Speed Blocks
- dual-port RAM option
• Improved VersaRing^TM I/O Interconnect for Better Fixed
- Fully PCI compliant (speed grades -2 and faster)
Pinout Flexibility
6
- Abundant flip-flops
• 12 mA Sink Current Per XC4000X Output
- Flexible function generators
• Flexible New High-Speed Clock Network
- Dedicated high-speed carry logic
- Eight additional Early Buffers for shorter clock delays
- Wide edge decoders on each edge
- Virtually unlimited number of clock signals
- Hierarchy of interconnect lines
• Optional Multiplexer or 2-input Function Generator on
- Internal 3-state bus capability
Device Outputs
- Eight global low-skew clock or signal distribution
• Four Additional Address Bits in Master Parallel
networks
Configuration Mode
• System Performance beyond 80 MHz
• XC4000XV Family offers the highest density with
• Flexible Array Architecture
0.25 µm 2.5 V technology
• Low Power Segmented Routing Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XC4000E output
• Configured by Loading Binary File
Introduction
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
- Unlimited re-programmability
• Read Back Capability
- Program verification
- Internal node observability
• Backward Compatible with XC4000 Devices
• Development System runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
The XC4000E and XC4000X Series currently have 20
members, as shown in Table 1.
May 14, 1999 (Version 1.6)
6-5