XC4013E Datasheet, PDF(23/68 Page) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4013E Datasheet, PDF (23/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays

~100 kâ¦

Z = DA â¢ A + DB â¢ B + DC â¢ C + DN â¢ N

BUFT

"Weak Keeper"

Figure 22: 3-State Buffers Implement a Multiplexer

BUFT

X6466

Wide Edge Decoders

Dedicated decoder circuitry boosts the performance of

wide decoding functions. When the address or data ï¬eld is

wider than the function generator inputs, FPGAs need

multi-level decoding and are thus slower than PALs.

XC4000 Series CLBs have nine inputs. Any decoder of up

to nine inputs is, therefore, compact and fast. However,

there is also a need for much wider decoders, especially for

address decoding in large microprocessor systems.

LUP symbol. Location attributes or properties such as L

(left edge) or TR (right half of top edge) should also be used

to ensure the correct placement of the decoder inputs.

INTERCONNECT

IOB

.I1

An XC4000 Series FPGA has four programmable decoders

located on each edge of the device. The inputs to each

decoder are any of the IOB I1 signals on that edge plus one

local interconnect per CLB row or column. Each row or col-

umn of CLBs provides up to three variables or their compli-

ments., as shown in Figure 23. Each decoder generates a

High output (resistor pull-up) when the AND condition of

the selected inputs, or their complements, is true. This is

analogous to a product term in typical PAL devices.

(

C) .....

(A â¢ B â¢ C) .....

Each of these wired-AND gates is capable of accepting up

to 42 inputs on the XC4005E and 72 on the XC4013E.

X2627

Figure 23: XC4000 Series Edge Decoding Example

There are up to 96 inputs for each decoder on the

XC4028X and 132 on the XC4052X. The decoders may

also be split in two when a larger number of narrower

OSC4

decoders are required, for a maximum of 32 decoders per

F8M

device.

F500K

The decoder outputs can drive CLB inputs, so they can be

combined with other logic to form a PAL-like AND/OR struc-

ture. The decoder outputs can also be routed directly to the

chip outputs. For fastest speed, the output should be on the

same chip edge as the decoder. Very large PALs can be

emulated by ORing the decoder outputs in a CLB. This

decoding feature covers what has long been considered a

weakness of older FPGAs. Users often resorted to external

PALs for simple but fast decoding functions. Now, the dedi-

cated decoders in the XC4000 Series device can imple-

ment these functions fast and efï¬ciently.

To use the wide edge decoders, place one or more of the

WAND library symbols (WAND1, WAND4, WAND8,

WAND16). Attach a DECODE attribute or property to each

WAND symbol. Tie the outputs together and attach a PUL-

F16K

F490

F15

X6703

Figure 24: XC4000 Series Oscillator Symbol

On-Chip Oscillator

XC4000 Series devices include an internal oscillator. This

oscillator is used to clock the power-on time-out, for conï¬g-

uration memory clearing, and as the source of CCLK in

Master conï¬guration modes. The oscillator runs at a nomi-

nal 8 MHz frequency that varies with process, Vcc, and

temperature. The output frequency falls between 4 and 10

MHz.

May 14, 1999 (Version 1.6)

6-27

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