XC4013E Datasheet, PDF (31/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
IOB inputs and outputs interface with the octal lines via the Two different types of clock buffers are available in the
single-length interconnect lines. Single-length lines are XC4000E:
also used for communication between the octals and dou-
ble-length lines, quads, and longlines within the CLB array.
• Primary Global Buffers (BUFGP)
• Secondary Global Buffers (BUFGS)
Segmentation into buffered octals was found to be optimal
for distributing signals over long distances around the
device.
Four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to poten-
Global Nets and Buffers
tially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs.
Both the XC4000E and the XC4000X have dedicated glo-
bal networks. These networks are designed to distribute
clocks and other high fanout control signals throughout the
devices with minimal skew. The global buffers are
The Primary Global buffers must be driven by the
semi-dedicated pads. The Secondary Global buffers can
be sourced by either semi-dedicated pads or internal nets.
described in detail in the following sections. The text ^{Each CLB column has four dedicated vertical Global lines.}
descriptions and diagrams are summarized in Table 15. ^{Each of these lines can be accessed by one particular Pri-}
The table shows which CLB and IOB clock pins can be ^{mary Global buffer, or by any of the Secondary Global buff-}
sourced by which global buffers.
ers, as shown in Figure 34. Each corner of the device has
In both XC4000E and XC4000X devices, placement of a ^{one Primary buffer and one Secondary buffer.}
library symbol called BUFG results in the software choos- ^{IOBs along the left and right edges have four vertical global}
ing the appropriate clock buffer, based on the timing ^{longlines. Top and bottom IOBs can be clocked from the}
requirements of the design. The detailed information in ^{global lines in the adjacent CLB column.}
these sections is included only for reference.
A global buffer should be specified for all timing-sensitive
Global Nets and Buffers (XC4000E only)
global signal distribution. To use a global buffer, place a
6
BUFGP (primary buffer), BUFGS (secondary buffer), or
Four vertical longlines in each CLB column are driven _{BUFG (either primary or secondary buffer) element in a}
exclusively by special global buffers. These longlines are _{schematic or in HDL code. If desired, attach a LOC}
in addition to the vertical longlines used for standard inter- _{attribute or property to direct placement to the designated}
connect. The four global lines can be driven by either of two _{location. For example, attach a LOC=L attribute or property}
types of global buffers. The clock pins of every CLB and _{to a BUFGS symbol to direct that a buffer be placed in one}
IOB can also be sourced from local interconnect.
of the two Secondary Global buffers on the left edge of the
device, or a LOC=BL to indicate the Secondary Global
buffer on the bottom edge of the device, on the left.
Table 15: Clock Pin Access
All CLBs in Quadrant
All CLBs in Device
IOBs on Adjacent Vertical
Half Edge
IOBs on Adjacent Vertical
Full Edge
IOBs on Adjacent Horizontal
Half Edge (Direct)
IOBs on Adjacent Horizontal
Half Edge (through CLB globals)
IOBs on Adjacent Horizontal
Full Edge (through CLB globals)
L = Left, R = Right, T = Top, B = Bottom
XC4000E
BUFGP BUFGS
√
√
√
√
√
√
√
√
√
√
√
√
BUFGLS
√
√
√
XC4000X
L&R
BUFGE
√
√
T&B
BUFGE
√
√
√
√
√
√
√
√
√
Local
Inter-
connect
√
√
√
√
√
√
√
May 14, 1999 (Version 1.6)
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