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XC4013E Datasheet, PDF (57/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays | |||
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the FPGA DIN input.
Each rising edge of the CCLK output increments the Serial
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble dataâand all
data that overï¬ows the lead deviceâon its DOUT pin.
There is an internal pipeline delay of 1.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In the bitstream generation software, the user can specify
Fast Conï¬gRate, which, starting several bits into the ï¬rst
frame, increases the CCLK frequency by a factor of eight.
For actual timing values please refer to âConï¬guration
Switching Characteristicsâ on page 68. Be sure that the
serial PROM and slaves are fast enough to support this
data rate. XC2000, XC3000/A, and XC3100A devices do
not support the Fast Conï¬gRate option.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is conï¬gured as user-I/O, but LDC is then
restricted to be a permanently High user output after con-
ï¬guration. Using DONE can also avoid contention on DIN,
provided the early DONE option is invoked.
Figure 51 on page 60 shows a full master/slave system.
The leftmost device is in Master Serial mode.
Master Serial mode is selected by a <000> on the mode
pins (M2, M1, M0).
CCLK
(Output)
2 TCKDS
1 TDSCK
6
Serial Data In
n
n+1
n+2
Serial DOUT
(Output)
nâ3
nâ2
nâ1
n
X3223
Description
Symbol
Min
Max
Units
CCLK
DIN setup
1
TDSCK
20
ns
DIN hold
2
TCKDS
0
ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conï¬guration by pulling PROGRAM
Low until Vcc is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 53: Master Serial Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
6-61
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