XC4013E Datasheet, PDF (10/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

R
XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C1 • • • C4
WE
D1
G1 • • • G4
4
D0
EC
DIN
WRITE
DECODER
4
1 of 16
16-LATCH
ARRAY
MUX
G'
LATCH
ENABLE
WRITE PULSE
READ
ADDRESS
DIN
F1 • • • F4
4
K
(CLOCK)
WRITE
DECODER
4
1 of 16
16-LATCH
ARRAY
MUX
F'
LATCH
ENABLE
WRITE PULSE
READ
ADDRESS
X6752
Figure 4: 16x2 (or 16x1) Edge-Triggered Single-Port RAM
4
C1 • • • C4
WE
G1 • • • G4
F1 • • • F4
EC
D1/A4
D0
EC
DIN
WRITE
16-LATCH
DECODER
ARRAY
MUX
4
4
1 of 16
LATCH
ENABLE
WRITE PULSE
READ
ADDRESS
DIN
K
(CLOCK)
WRITE
16-LATCH
DECODER
ARRAY
MUX
4
4
1 of 16
LATCH
ENABLE
WRITE PULSE
READ
ADDRESS
Figure 5: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)
G'
H'
F'
X6754
6-14
May 14, 1999 (Version 1.6)