DS588 Datasheet, PDF (4/24 Pages) Xilinx, Inc – Programmable interrupt generation

XPS Delta-Sigma Digital to Analog Converter (DAC) (v1.01a)
• Output Source and Sink Current: Unlike normal digital applications, it is important that signal
DACout always switch the entire voltage range from 0 V to V_CCO (rail-to-rail). If the value of R is
too low and signal DACout can not switch rail-to-rail, the analog output is non-linear; i.e., the
absolute output voltage change resulting from incrementing or decrementing DACin is not
constant. The worst-case output impedance of the 24 mA LVTTL buffer is about 25 W. R must be
2.5 KW or greater to ensure rail-to-rail switching, with an error of 1% or less.
• Load Impedance: Keep the value of R low relative to the impedance of the load so that the current
change through the capacitor due to loading becomes negligible.
• Time Constant: The filter time constant (τ = RC) must be high enough to greatly attenuate the
individual pulses in the pulse string. On the other hand, a high time constant may also attenuate
the desired low-frequency output signal. These potentially conflicting requirements are analyzed
separately.
Pulse String Filtering
In the midrange voltages, signal DACout is switching rapidly, making it relatively easy to filter. When
the DAC input is at 1 or the highest possible value, the signal DACoutDrvr is at the same level for all
but one CLK cycle for each sample period. These are the most difficult output strings to filter; i.e., they
are the worst case.
Although the filter noise may be calculated as an absolute peak-to-peak voltage, it is more useful to
consider it as a fraction of the step voltage. The step voltage (V_S) is defined as the absolute change in
V_OUT when the DAC input is incremented or decremented. For an 8-bit DAC, V_S equals (1/256) x
V_CCO.
The worst-case peak-to-peak filter noise for an 8-bit DAC can be expressed as follows:
PPN_FS = (1-e^-(1/fτ)) x ((1-e^-(255/fτ))/(1-e^-(256/fτ))) x 256
where:
PPN_FS is peak-to-peak noise expressed as a fraction of step voltage
f is the DAC clock frequency
τ is the filter time constant, RC.
For simplicity, we did not generalize this equation to handle any width DAC. For other widths, the
equation for worst-case peak-to-peak noise is,
PPN_FS = (1-e^-(1/fτ)) x ((1-e^-(y/fτ))/(1-e^-(z/fτ))) x z
where:
y = 2 ^{C_NUM_DAC_BITS} - 1
z = 2 ^{C_NUM_DAC_BITS}
This equation was used to create Figure 3, Figure 4 and Figure 5. These charts may be used to
determine the value of RC for the desired worst-case noise voltage and operating frequency. For
example, for an 8-bit DAC with a clock frequency of 80 MHz, the user might choose an RC value of
13.0x10^-6, corresponding to a peak-to-peak noise voltage of about 0.25 V_S. This leaves 0.75 V_S noise
margin between steps. Part of this noise margin is needed to handle other noise sources such as noise
on V_CCO.
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DS588 December 2, 2009
Product Specification