DS588 Datasheet, PDF (21/24 Pages) Xilinx, Inc – Programmable interrupt generation

XPS Delta-Sigma Digital to Analog Converter (DAC) (v1.01a)
The XPS Delta-Sigma DAC resource utilization for various parameter combinations measured with the
Spartan-6 FPGA as the target device are detailed in Table 14.
Table 14: Performance and Resource Utilization Benchmarks on the Spartan-6 FPGA
(xc6slxt100-2-fgg676)
Parameter Values
Device Resources
Performanc
e
2
0
1
1
32
1
53
88
110
100
4
0
4
0
64
2
82
161
155
110
8
0
8
0
128
3
95
192
185
110
8
1
8
0
128
3
95
196
186
100
16
0
8
0
64
3
99
232
206
100
16
1
16
0
128
4
100
262
218
100
System Performance
To measure the system performance (F_MAX) of this core, this core was added to a Virtex-4 FPGA system,
a Virtex-5 FPGA system, and a Spartan-3A DSP FPGA system as the Device Under Test (DUT) as
shown in Figure 13, Figure 14, and Figure 15.
Because the XPS Delta-Sigma DAC core will be used with other design modules in the FPGA, the
utilization and timing numbers reported in this section are estimates only. When this core is combined
with other designs in the system, the utilization of FPGA resources and timing of the core design will
vary from the results reported here.
X-Ref Target - Figure 13
PLBV46
PLBV46
MPMC5
XPS CDMA
XPS CDMA
Device Under
Test (DUT)
IPLB1 DPLB1
PowerPC ^® 405 DPLB0
Processor
IPLB0
PLBV46
XPS BRAM XPS INTC XPS GPIO
Figure 13: Virtex-4 FX FPGA System
XPS UART
Lite
DS588_13_100909
DS588 December 2, 2009
www.xilinx.com
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Product Specification