DS588 Datasheet, PDF (2/24 Pages) Xilinx, Inc – Programmable interrupt generation

XPS Delta-Sigma Digital to Analog Converter (DAC) (v1.01a)
Functional Description
A Delta-Sigma DAC uses digital techniques to convert a digital number into an analog voltage.
Consequently, it is impervious to temperature change, and may be implemented in programmable
logic. Delta-Sigma DACs are actually high-speed single-bit DACs. Using digital feedback, a string of
pulses is generated. The average duty cycle of the pulse string is proportional to the value of the binary
input. The analog signal is created by passing the pulse string through an analog low-pass filter. While
an in-depth discussion of Delta-Sigma conversion is beyond the scope of this document, the basic
architecture, implementation, and trade-offs are covered.
Delta-Sigma Architecture
Figure 1 is a top-level block diagram of a typical Delta-Sigma DAC implementation. As shown in this
diagram, the inputs include reset and clock signals, in addition to the binary number bus.
DACoutDrvr drives an external low-pass filter. V_OUT can be set from 0 V to V_CCO, where V_CCO is the
supply voltage applied to the FPGA I/O bank driving the resistor-capacitor filter.
X-Ref Target - Figure 1
Virtex FPGA
DACin
DAC_Clk
Reset
DAC
Module
DACin
Reset
DACout
3.3k
Vout
0.0047 x 10^-6 F
Figure 1: DAC Module
DS588_01_100909
The classic current summing digital to analog converter uses matched resistors to convert a binary
number to a corresponding voltage level. This technique works well for high-speed DACs when the
binary number is up to ten bits wide. However, it is difficult to maintain accuracy over a range of
temperatures as the number of bits increases.
Delta-Sigma DACs are used extensively in audio applications. They are suited for low frequency
applications that require relatively high accuracy.
As is standard practice, the DAC binary input in this implementation is an unsigned number with zero
representing the lowest voltage level. The analog voltage output is also positive only. A zero on the
input produces zero volts at the output. All ones on the input cause the output to nearly reach V_CCO.
For AC signals, the positive bias on the analog signal can be removed with capacitive coupling to the
load. Figure 2 is the detailed block diagram of the XPS Delta-Sigma DAC. The width of the binary input
in the implementation described below is configurable. For simplicity, the block diagram depicts a
DAC with an 8-bit binary input.
The term, Delta-Sigma, refers to the arithmetic difference and sum, respectively. In this implementation,
binary adders are used to create both the difference and the sum. Although the inputs to the Delta
adder are unsigned, the outputs of both adders are considered signed numbers.
The Delta Adder calculates the difference between the DAC input and the current DAC output,
represented as a binary number. Since the DAC output is a single bit, it is “all or nothing”; i.e., either all
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DS588 December 2, 2009
Product Specification