DS588 Datasheet, PDF (14/24 Pages) Xilinx, Inc – Programmable interrupt generation

XPS Delta-Sigma Digital to Analog Converter (DAC) (v1.01a)
XPS Delta-Sigma DAC Port Dependencies
The dependencies between the XPS Delta-Sigma DAC core design parameters and I/O signals are
described in Table 3. In addition, when certain features are parameterized out of the design, the related
logic will no longer be a part of the design. The unused input signals and related output signals are set
to a specified value.
Table 3: XPS Delta-Sigma DAC Parameter Port Dependencies
Generic
Name
Affects Depends
Relationship Description
Design Parameters
G4 C_SPLB_DWIDTH
P8, P11,
P34
-
Width of the PLB Data Bus and PLB Slave
Data Bus
G5 C_SPLB_AWIDTH
P4
-
Width of the PLB Address Bus
G7 C_SPLB_MID_WIDTH
P6
G8
log₂(C_SPLB_NUM_MASTERS) with a
minimum value of 1
I/O Signals
P4
PLB_ABus[0 :
C_SPLB_AWIDTH - 1]
-
G5
Width of the PLB Address Bus varies
according to C_SPLB_AWIDTH
P6
PLB_masterID[0 :
C_SPLB_MID_WIDTH - 1]
-
G7
Width of the PLB_mastedID varies according
to C_SPLB_MID_WIDTH
P8
PLB_BE[0 :
[C_SPLB_DWIDTH/8] - 1]
-
G4
Width of the PLB Byte Enable varies
according to C_SPLB_DWIDTH
P11
PLB_wrDBus[0 :
C_SPLB_DWIDTH - 1]
-
G
Width of the PLB WriteData Bus varies
according to C_SPLB_DWIDTH
P34
Sl_rdBus[0 :
C_SPLB_DWIDTH - 1]
-
G4
Width of the Slave Read Data Bus varies
according to C_SPLB_DWIDTH
Sl_MBusy[0 :
P37 C_SPLB_NUM_MASTERS
-
- 1]
G8
Width of the Sl_MBusy varies according to
C_SPLB_NUM_MASTERS
Sl_MWrErr[0 :
P38 C_SPLB_NUM_MASTERS
-
- 1]
G8
Width of the Sl_MWrErr varies according to
C_SPLB_NUM_MASTERS
Sl_MRdErr[0 :
P39 C_SPLB_NUM_MASTERS
-
- 1]
G8
Width of the Sl_MRdErr varies according to
C_SPLB_NUM_MASTERS
XPS Delta-Sigma DAC Register Descriptions
The internal registers of the XPS Delta-Sigma DAC are offset from the base address C_BASEADDR. The
XPS Delta-Sigma DAC internal register set is described in Table 4.
Table 4: XPS Delta-Sigma DAC Registers
Register Name
Address
Access
Device Global Interrupt Enable Register (GIE)
C_BASEADDR + 0x01C Read/Write
IP Interrupt Status Register (IPISR)
C_BASEADDR + 0x020 Read/Write
IP Interrupt Enable Register (IPIER)
C_BASEADDR + 0x028 Read/Write
Control Register (CR)
C_BASEADDR + 0x100 Read/Write
Data FIFO (FIFO)
C_BASEADDR + 0x104 Read/Write
14
www.xilinx.com
DS588 December 2, 2009
Product Specification