DS588 Datasheet, PDF (3/24 Pages) Xilinx, Inc – Programmable interrupt generation

XPS Delta-Sigma Digital to Analog Converter (DAC) (v1.01a)
zeroes or all ones. As shown in Figure 2, the difference will result when adding the input to a value
created by concatenating two copies of the most significant bit of the Sigma Latch with all zeros.
This also compensates for the fact that DACin is unsigned. The Sigma Adder sums its previous output,
held in Sigma Latch, with the current output of the Delta Adder. In most cases, the Delta adder is
optimized out when the high level design is synthesized.
This is because all bits on either the A or B inputs are zero, so A and B are simply merged, rather than
added. As noted below, the DAC input can be widened by one bit to allow the full analog range of 0V
to VCCO. In this case, the Delta adder is needed.
X-Ref Target - Figure 2
IP2INTC_Irpt
Interrupt Service Controller
DAC Module
PLB
PLB
SPLB_Rst _Interface
Module
SPLB_Clk
Register
Interface ^{DACin 8}
Delta
Adder
A
D
Sum
SRL
FIFO
DeltaB
B
Sigma
10 ^Adder
A
Sum ¹⁰
S
B
RESET
READ_EN
DAC_Clk_EN
10
10
{L [0], L [0], 0, 0, 0, 0, 0, 0, 0, 0}
Sigma
Latch
L
D
Q
CE _Init
L [0]
D
CE
DACout
Q
CLR
L [0]
Figure 2: XPS Delta-Sigma DAC Internal Block Diagram
DS588_02_100909
For the implementation in Figure 1, the output voltage (VOUT) as a function of the DAC input may be
expressed as follows:
V_OUT = (DACin/(2^{(C_NUM_DAC_BITS)})) x V_CCO Volts
For example, for an 8-bit DAC (C_NUM_DAC_BITS = 8) the lowest V_OUT is 0 V when DACin is 0x00.
The highest V_OUT is 255/256*V_CCO volts when DACin is 0xFF.
For some applications, it may be important for V_OUT to swing through the entire voltage range: 0 V to
V_CCO (rail-to-rail). This is accomplished by using the C_FULL_RANGE generic which increases the
DACin bus width by one bit and leaving all other bus widths the same. For an 8-bit DAC with an input
value of 256, V_OUT = V_CCO. Note for C_NUM_DAC_BITS = 8 that all DAC in values greater than 256
are illegal and should not be used. The valid range of digital inputs for given values of
C_NUM_DAC_BITS and C_FULL_RANGE is given as 0x0 to 0x(2^{(C_NUM_DAC_BITS)} -1 +
C_FULL_RANGE), where 2^{(C_NUM_DAC_BITS)} is always greater than or equal to (2^{(C_NUM_DAC_BITS)} -1
+ C_FULL_RANGE).
As outlined in this specification, it is often advantageous to use a high-frequency clock. The desired
clock may be faster than that which can be practically sourced externally.
Low-Pass Filter
The resistor/capacitor low-pass filter shown in Figure 1 is adequate for most applications. A 24 mA
LVTTL output buffer is used to provide maximum current drive.
There are three primary considerations in choosing values for the resistor and capacitor:
DS588 December 2, 2009
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Product Specification