DS588 Datasheet, PDF (17/24 Pages) Xilinx, Inc – Programmable interrupt generation

XPS Delta-Sigma Digital to Analog Converter (DAC) (v1.01a)
XPS Delta-Sigma DAC Interrupt Descriptions
Interrupts
The interrupt signals generated by the XPS Delta-Sigma DAC are managed by the Interrupt Service
Controller (ISC). This unit provides many of the features commonly provided for interrupt handling.
The IPIER and IPISR contain the bit mapping as shown in Figure 11. Please refer to the Processor IP
Reference Guide under Part 1 for a complete description of the GIE, IPISR and IPIER. The XPS Delta-
Sigma DAC has two unique interrupts that are sent to the CPU. The number in the parenthesis is the
interrupt bit number.
X-Ref Target - Figure 11
FIFO PIRQ
0
29 30 31
Figure 11: Interrupt Mapping
FIFO EMPTY
DS588_11_100909
Table 9: Data FIFO Interrupt Register Bit Definitions
Bit(s)
Name
Access
Reset
Value
Description
0 - 29 Reserved
NA
-
Reserved
30 FIFO EMPTY
Read/Write
0
This interrupt will be set and remain set as long the Data
FIFO is empty.
31 FIFO PIRQ
This interrupt will be set and remain set as long the PIRQ
Read/Write
0
is equal to, or greater than the OCCY. Clearing this
interrupt requires that the Data FIFO be filled to a value
greater than PIRQ.
Flow Description
The subsequent steps are required to set the DAC registers to initiate a conversion.
1. Initialize the interrupt registers GIE and IPIER as required, if interrupts are to be used. See the
Processor IP Reference Guide for a complete description of the interrupt registers.
2. Write the data to be converted into the Data FIFO.
3. Set the PIRQ to generate an interrupt before the FIFO is empty.
4. Enable the DAC by writing a ’1’ to the control register.
5. Drive Read_en high for one SPLB_Clk. The first value written into the Data FIFO will start being
converted two Dac_Clk_en later.
6. After the appropriate number of DAC_Clk_en have occurred drive the Read_en high for one clock
and the next value will start being converted two Dac_Clk_en later.
7. If the Read_en signal is high and the Data FIFO is empty the DACout will be driven to ’0’. DACout
will remain zero until data is written to the Data FIFO and a Read_en occurs.
DS588 December 2, 2009
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Product Specification