DS588 Datasheet, PDF (18/24 Pages) Xilinx, Inc – Programmable interrupt generation

XPS Delta-Sigma Digital to Analog Converter (DAC) (v1.01a)
Timing Diagram
Following diagram shows the generation of the control signals for the conversion.
X-Ref Target - Figure 12
SPLB_Clk
See Note 1
Read_En
DAC_Clk_En
DACout
Note 1:
Drive Read)en High for one SPLB_Clk. The first value written into the Data FIFO will start
being converted two Dac_Clk_en later. Read_en should be generated if the FIFO is non-empty.
Figure 12: Control Signal Generation for DAC
DS588_12_10909
Design Implementation
Device Utilization and Performance Benchmarks
Core Performance
Since the XPS Delta-Sigma DAC core will be used with other design modules in the FPGA, the
utilization and timing numbers reported in this section are estimates only. When the XPS Delta-Sigma
DAC core is combined with other designs in the system, the utilization of FPGA resources and timing
of the XPS Delta-Sigma DAC design will vary from the results reported here.
The XPS Delta-Sigma DAC resource utilization for various parameter combinations measured with the
Virtex-4 FPGA as the target device are detailed in Table 10
Table 10: Performance and Resource Utilization Benchmarks on the Virtex-4 FPGA
(xc4vlx25-ff668-11)
Parameter Values
Device Resources
Performanc
e
2
0
1
1
32
1
165
143
175
198
4
0
4
0
64
2
240
237
170
198
8
0
8
0
128
3
287
295
200
186
18
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DS588 December 2, 2009
Product Specification