DS588 Datasheet, PDF (22/24 Pages) Xilinx, Inc – Programmable interrupt generation

XPS Delta-Sigma Digital to Analog Converter (DAC) (v1.01a)
X-Ref Target - Figure 14
MMicircoroBBla_lazeze®
Processor
PLBV46
PLBV46
XCL
XCL
MPMC5
XPS CDMA
XPS CDMA
Device Under
Test (DUT
X-Ref Target - Figure 15
PowerPC ^® 405
Processor
MC
PPC440
MC DDR2
PLBV46
MDM
XPS INTC
XPS BRAM
XPS UART
Lite
MDM
Figure 14: Virtex-5 FX FPGA System
DS588_14_100909
MPMC5
XPS CDMA
XPS CDMA
Device Under
Test (DUT)
MicroBlaze ^®
Processor
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
Figure 15: Spartan-3A DSP FPGA System
MDM
DS588_15_100909
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately
70% and the I/O utilization to approximately 80%. Using the default tool options and the slowest speed
grade for the target FPGA, the resulting target F_MAX numbers are shown in Table 15.
Table 15: XPS Delta-Sigma DAC System Performance
Target FPGA
S3D3400 -4
Target F_MAX (MHz)
100
V4LX25 -11
125
V5FXT70 -1
150
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed
value across all systems.
22
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DS588 December 2, 2009
Product Specification