DS588 Datasheet, PDF (15/24 Pages) Xilinx, Inc – Programmable interrupt generation

XPS Delta-Sigma Digital to Analog Converter (DAC) (v1.01a)
Table 4: XPS Delta-Sigma DAC Registers (Cont’d)
Register Name
Data FIFO Occupancy (OCCY)
Data FIFO programmable depth interrupt Register (PIRQ)
Address
C_BASEADDR + 0x108
C_BASEADDR + 0x10C
Access
Read
Read/Write
Control Register (CR)
The bit definitions for the register are shown inTable 5. The enable bit (EN) when set to "0"will prevent
the XPS Delta-Sigma DAC from creating a pulse string, and the Dac_out will be zero.
X-Ref Target - Figure 7
Reserved
EN
0
29 30 31
Figure 7: XPS Delta-Sigma DAC Control Register
FIFO_RST
DS588_07_100909
Table 5: XPS Delta-Sigma DAC Control Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0- 29 Reserved
-
NA
Reserved.
30
FIFO_RST Read/Write
FIFO Reset
’0’
’1’ = Resets the Data FIFO.
’0’ = Data FIFO normal operation.
DAC Enable
31
EN
Read/Write
’0’
’1’ = Enables the XPS Delta-Sigma DAC.
’0’ = Resets and disables the XPS Delta-Sigma DAC. The
DAC output will be zero.
Data FIFO
This 16 entry deep SRL FIFO contains data to be output by the XPS Delta-Sigma DAC. The Data FIFO
is shown in Table 6. Reading of this location will result in reading the current word being output from
the FIFO. Attempting to write to a full FIFO is not recommended and results in that data byte being
lost.
When the Data FIFO is empty and the DAC is enabled, the DAC output will be zero.
Figure 8 shows the location for data on the PLB when C_NUM_DAC_BITS is set to 8 and
C_FULL_RANGE is set to 0. If C_FULL_RANGE is set to 1 and C_NUM_DAC_BITS is set to 8 then data
bits 23 through 31 will be used, but any value greater than 0X100 will result in an undefined DAC
output.
X-Ref Target - Figure 8
Reserved
Data
0
23 24
31
DS588_08_100909
Figure 8: Data FIFO
DS588 December 2, 2009
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Product Specification