DS588 Datasheet, PDF (11/24 Pages) Xilinx, Inc – Programmable interrupt generation

XPS Delta-Sigma Digital to Analog Converter (DAC) (v1.01a)
• Analog to Digital Conversion: This DAC may be used as a voltage reference in an ADC. See
XILINX application note XAPP155 (Analog to Digital Converter) for a complete discussion of this
application.
XPS Delta-Sigma DAC I/O Signals
The XPS Delta-Sigma DAC I/O signals are listed and described in Table 1.
Table 1: XPS Delta-Sigma DAC I/O Signals
Port
Signal Name
Interface
I/O
Initial
State
Description
System Signals
P1 IP2INTC_Irpt
System
O
0 System interrupt
P2 SPLB_Clk
PLB
I
- PLB clock
P3 SPLB_Rst
PLB
I
- PLB reset
PLB Master Interface Signals
P4
PLB_ABus[0 :
C_SPLB_AWIDTH]
PLB
I
- PLB address bus
P5 PLB_PAValid
PLB
I
- PLB primary address valid indicator
PLB_masterID[0 :
P6 C_SPLB_MID_WIDTH
PLB
- 1]
I
- PLB current master identifier
P7 PLB_RNW
PLB
I
- PLB read not write
PLB_BE[0 :
P8 C_SPLB_DWIDTH/8 -
PLB
1]
I
- PLB byte enables
P9 PLB_size[0 : 3]
PLB
I
- PLB transfer size
P10 PLB_type[0 : 2]
PLB
I
- PLB transfer type
P11
PLB_wrDBus[0 :
C_SPLB_DWIDTH - 1]
PLB
I
- PLB write data bus
Unused PLB Master Interface Signals
P12 PLB_UABus[0 : 31]
PLB
I
- PLB upper address bits
P13 PLB_SAValid
PLB
I
- PLB secondary address valid
P14 PLB_rdPrim
PLB
I
-
PLB secondary to primary read request
indicator
P15 PLB_wrPrim
PLB
I
-
PLB secondary to primary write request
indicator
P16 PLB_abort
PLB
I
- PLB abort bus request
P17 PLB_busLock
PLB
I
- PLB bus lock
P18 PLB_MSize[0 : 1]
PLB
I
- PLB data bus width indicator
P19 PLB_TAttribute[0 : 15]
PLB
I
- PLB transfer attribute
P20 PLB_lockerr
PLB
I
- PLB lock error
P21 PLB_wrBurst
PLB
I
- PLB burst write transfer
P22 PLB_rdBurst
PLB
I
- PLB burst read transfer
P23 PLB_wrPendReq
PLB
I
- PLB pending bus write request
P24 PLB_rdPendReq
PLB
I
- PLB pending bus read request
DS588 December 2, 2009
www.xilinx.com
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Product Specification