W79E225A_08 Datasheet, PDF (95/203 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/226A/227A Data Sheet
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts sampled in the same machine cycle. If an interrupt
flag is active in one cycle but not responded to, and is not active when the above conditions are met,
the denied interrupt will not be serviced. This means that active interrupts are not remembered; every
polling cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate
service routine. This may or may not clear the flag which caused the interrupt. In case of Timer
interrupts, the TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the
appropriate timer service routine. In case of external interrupt, INT0 and INT1, the flags are cleared
only if they are edge triggered. In case of Serial interrupts, the flags are not cleared by hardware. In
the case of Timer 2 interrupt, the flags are not cleared by hardware. The Watchdog timer interrupt flag
WDIF has to be cleared by software. The hardware LCALL behaves exactly like the software LCALL
instruction. This instruction saves the Program Counter contents onto the Stack, but does not save the
Program Status Word PSW. The PC is reloaded with the vector address of that interrupt which caused
the LCALL. These address of vector for the different sources are shown in Table 11- 1: Priority structure of
interrupts.
PRIORITY BITS
IPH/EIPH/EIP1H
IP/EIP/EIP1
INTERRUPT PRIORITY LEVEL
0
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest priority)
Table 11- 2: Four-level interrupt priority
Each interrupt source can be individually programmed to one of four priority levels by setting or
clearing bits in the IP, IPH, EIP, EIPH, EIP1 and EIP1H registers. An interrupt service routine in
progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or
lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source.
So, if two requests of different priority levels are received simultaneously, the request of higher priority
level is serviced.
If requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. This is called the arbitration ranking. Note that the arbitration
ranking is only used to resolve simultaneous requests of the same priority level.
As below Table summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits,
arbitration ranking, and whether each interrupt may wake up the CPU from Power Down mode.
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Publication Release Date: April 15, 2008
Revision A4.0