W79E225A_08 Datasheet, PDF (68/203 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/226A/227A Data Sheet
BIT NAME
7 SSOE
6 SPE
5 LSBFE
4 MSTR
3 CPOL
2 CPHA
1-0 SPR
FUNCTION
Slave Select Output Enable Bit. The SS output feature is enabled only in master
mode by asserting the SSOE bit. In slave mode (/SS) input is not affected by
SSOE bit. See table below.
Serial Peripheral System Enable Bit.
When the SPE bit is set, SPI block functions is enable. When MODF is set, SPE
always reads 0.
0 = SPI system disabled.
1 = SPI system enabled.
LSB - First Enable. This bit does not affect the position of the MSB and LSB in
the data register. Reads and writes of the data register always have the MSB in
bit 7. In master mode, a change of this bit will abort a transmission in progress
and force the SPI system into idle state.
1 = Data is transferred least significant bit first.
0 = Data is transferred most significant bit first.
Master Mode Select Bit. It is customary to have an external pull-up resistor on
lines that are driven by open drain devices.
0 = Slave mode.
1 = Master mode.
Clock Polarity Bit. When the clock polarity bit is cleared and data is not being
transferred, the SPCLK pin of the master device has a steady state low value.
When CPOL is set, SPCLK idles high.
CPHA Clock Phase Bit. The clock phase bit, in conjunction with the CPOL bit,
controls the clock-data relationship between master and slave. The CPHA bit
selects one of two different clocking protocols.
SPI Baud Rate Selection Bits. These bits specify the SPI baud rates.
DRSS SSOE
MASTER MODE
SLAVE MODE
0
0
/SS input ( With Mode Fault )
/SS Input ( Not affected by SSOE )
0
1
Reserved
/SS Input ( Not affected by SSOE )
1
0
/SS General purpose I/O ( No Mode
Fault )
/SS Input ( Not affected by SSOE )
1
1
/SS output ( No Mode Fault )
/SS Input ( Not affected by SSOE )
Note: In master mode, a change of LSBFE, MSTR, CPOL, CPHA and SPR [1:0] will abort a
transmission in progress and force the SPI system into idle state.
SERIAL PERIPHERAL STATUS REGISTER
Bit:
7
6
5
4
3
2
1
0
SPIF
WCOL
SPIOVF MODF
DRSS
-
-
-
Mnemonic: SPSR
Address: F4h
- 68 -
Publication Release Date: April 15, 2008
Revision A4.0