W79E225A_08 Datasheet, PDF (104/203 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/226A/227A Data Sheet
13. WATCHDOG TIMER
The Watchdog Timer is a free-running timer that can be programmed to serve as a system monitor, a
time-base generator or an event timer. It is basically a set of dividers that divide the system clock to
determine the time-out interval. When the time-out occurs, a flag is set, which can generate an
interrupt or a system reset, if enabled. The interrupt will occur if its interrupt and global interrupt
enables are set. The interrupt and reset functions are independent of each other and may be used
separately or together.
The main use of the Watchdog Timer is as a system monitor. In case of power glitches or
electromagnetic interference, the processor may begin to execute errant code. The Watchdog Timer
helps W79E22X SERIES recovers from these states. During development, the code is first written
without the watchdog interrupt or reset. Then, the watchdog interrupt is enabled to identify code
locations where the interrupt occurs, and instructions are inserted to reset the Watchdog Timer in
these locations. In the final version, the watchdog interrupt is disabled, and the watchdog reset is
enabled. If errant code is executed, the Watchdog Timer is not reset at the required times, so a
Watchdog Timer reset occurs.
When used as a simple timer, the reset and interrupt functions are disabled. The Watchdog Timer can
be started by RWT and sets the WDIF flag after the selected time interval. Meanwhile, the program
polls the WDIF flag to find out when the selected time interval has passed. Alternatively, the Watchdog
Timer can also be used as a very long timer. In this case, the interrupt feature is enabled.
Figure 13-1: Watchdog Timer
The Watchdog Timer should be started by RWT because this ensures that the timer starts from a
known state. The RWT bit is self-clearing; i.e., after writing a 1 to this bit, the bit is automatically
cleared. After setting RWT, the Watchdog Timer begins counting clock cycles. The time-out interval is
selected by WD1 and WD0 (CKCON.7 and CKCON.6).
WD1
0
0
1
1
WD0
0
1
0
1
INTERRUPT
TIME-OUT
2¹⁷
2²⁰
2²³
2²⁶
RESET
TIME-OUT
2¹⁷ + 512
2²⁰ + 512
2²³ + 512
2²⁶ + 512
NUMBER OF
CLOCKS
131072
1048576
8388608
67108864
TIME
@ 10 MHZ
13.11 mS
104.86 mS
838.86 mS
6710.89 mS
TIME
@ 11.0592 MHZ
11.85 mS
94.81 mS
758.52 mS
6068.15 mS
Table 13-1: Time-out values for the Watchdog Timer
TIME
@ 25 MHZ
5.24 mS
41.94 mS
335.54 mS
2684.35 mS
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Publication Release Date: April 15, 2008
Revision A4.0