W79E225A_08 Datasheet, PDF (169/203 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/226A/227A Data Sheet
DRSS SSOE
MASTER MODE
0
0 SS input ( With Mode Fault )
0
1 Reserved
1
0 _SS General purpose I/O ( No Mode Fault )
1
1 _SS output ( No Mode Fault )
SLAVE MODE
SS Input ( Not affected by SSOE )
SS Input ( Not affected by SSOE )
SS Input ( Not affected by SSOE )
SS Input ( Not affected by SSOE )
During master mode (with SSOE=DRSS= 0), mode fault will be set if SS pin is detected low. When
mode fault is detected hardware will clear MSTR bit and SPE bit in the meantime it will also generated
interrupt request, if ESPI is enabled.
Figure 18-10: SPI interrupt request
18.3.5 SPI I/O pins mode
When SPI is disabled (SPE = 0) the corresponding I/O is following the original setting and act as a
normal I/O. In the case of SPI is enabled (SPE = 1) the SPI pins I/O mode follow the below table. For
SS pin it is always at Quasi-bidirectional mode whether it is configured as master or slave.
MISO
Master Input
Slave
Output** during /SS = Low
Else Input mode
Input = Quasi-bidirectional mode
Output = Push-pull mode
MOSI
Output
CLK
Output
/SS
Output*: DRSS=0,SSOE=0
Input: DRSS=1, SSOE=1
Input Input Input
Output* = this output mode in /SS is Quasi-bidirectional output mode. Master needs to detect
mode fault during master outputs /SS low.
Output** = In SLAVE mode, MISO is in output mode only during the time of SS =Low,
otherwise it must keep in input mode (Quasi-bidirectional).
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Publication Release Date: April 15, 2008
Revision A4.0