W79E225A_08 Datasheet, PDF (143/203 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/226A/227A Data Sheet
16. SERIAL PORT
The W79E22X SERIES has two enhanced serial ports that are functionally similar to the serial port of
the original 8052 family. Both the serial ports are full-duplex ports, and the W79E22X SERIES
provides additional features, such as Frame Error Detection and Automatic Address Recognition. The
serial port 0 can use Timer 1 or 2 as baud rate generator, but the serial port 1 only uses Timer 1 as
baud rate generator. However, note that if both serial ports are enabled the baud rate setting control of
UART1 is also from the setting of UART0. The serial ports are capable of synchronous and
asynchronous communication. In synchronous mode, the W79E22X SERIES generates the clock and
operates in half-duplex mode. In asynchronous mode, the serial ports can simultaneously transmit and
receive data. The transmit registers and the receive buffers are both addressed as SBUF (SBUF1 for
the second serial port), but any write to SBUF/SBUF1 writes to the transmit register while any read
from SBUF/SBUF1 reads from the receive buffer. Both serial ports can operate in four modes, as
described below. The descriptions are for serial port 0, however, it also apply to the second serial port.
16.1 Mode 0
This mode provides half-duplex, synchronous communication with external devices. In this mode,
serial data is transmitted and received on the RXD line, and the W79E22X SERIES provides the shift
clock on TxD, whether the device is transmitting or receiving. Eight bits are transmitted or received per
frame, LSB first. The baud rate is 1/12 or 1/4 of the oscillator frequency, as determined by the SM2 bit
(SCON.5; 0 = 1/12; 1 = 1/4). This programmable baud rate is the only difference between the standard
8051/52 and the W79E22X SERIES in mode 0.
Any write to SBUF starts transmission. The shift clock is activated, and data is shifted out on RxD until
all eight bits are transmitted. If SM2 is 1, the data appears on RxD one clock period before the falling
edge of the shift clock on TxD. Then, the clock remains low for two clock periods before going high
again. If SM2 is 0, the data appears on RxD three clock periods before the falling edge of the shift
clock on TxD, and the clock on TxD remains low for six clock periods before going high again. This
ensures that, at the receiving end, the data on the RxD line can be clocked on the rising edge of the
shift clock or latched when the clock is low. The TI flag is set high in C1 following the end of
transmission. The functional block diagram is shown below.
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Publication Release Date: April 15, 2008
Revision A4.0