W79E225A_08 Datasheet, PDF (183/203 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/226A/227A Data Sheet
23. OPTION BITS
This device has two CONFIG bits (CONFIG0, CONFIG1) that must be define at power up and can not
be set after the program start of execution. Those features are configured through the use of two flash
EPROM bytes, and the flash EPROM can be programmed and verified repeatedly. Until the code
inside the Flash EPROM is confirmed OK, the code can be protected. The protection of flash EPROM
and those operations of the configuration bits are described below.
23.1 Config0
BIT
DESCRIPTION
B0 =0: Lock data out
B1 =0: MOVC Inhibited
B2 =0; 1/2/2K Data Flash EPROM lock bit
B3 Reserved
=1: Disable H/W reboot by P3.6 and P3.7
B4
=0: Enable H/W reboot by P3.6 and P3.7
=1: Disable H/W reboot by P4.3
B5 =0: Enable H/W reboot by P4.3
Note: Support in 48L LQFP package only.
B6 Reserved
=1: Crystal > 24MHz
B7
=0: Crystal < 24MHz
Table 23-1 Config0 Option Bits
B0: Lock bit
This bit is used to protect the customer's program code in the W79E22X SERIES. After the
programmer finishes the programming and verifies sequence B0 can be cleared to logic 0 to protect
code from reading by any access path. Once this bit is set to logic 0, both the Flash EPROM data and
Special Setting Registers can not be accessed again.
B1: MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
B4: H/W Reboot with P3.6 and P3.7
If this bit is set to logic 0, enable to reboot 4k LD Flash mode while RST =H, P3.6 = L and P3.7 = L
state. CPU will start from LD Flash to update the user’s program.
B5: H/W Reboot with P4.3
If this bit is set to logic 0, enable to reboot 4k LD Flash mode while RST =H and P4.3 = L state. CPU
will start from LD Flash to update the user’s program
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Publication Release Date: April 15, 2008
Revision A4.0