W79E225A_08 Datasheet, PDF (10/203 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/226A/227A Data Sheet
5. PIN DESCRIPTION
SYMBOL
EA
TYPE
I
INITIAL
STATE
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to
execute from external ROM. The ROM address and data are not
presented on the bus if the EA pin is high.
Note: This pin has no internal pull-up or pull-down. The pin
-
needs externally pull-up to execute from internal APROM. For
executing from external APROM, the pin needs externally pull-
down. The pin state is internally latched during all reset. User
needs to take note that changes to /EA pin state after reset will
not be effective.
PSEN
OH
High
PROGRAM STORE ENABLE: PSEN enables the external ROM
data in the Port 0 address/data bus. When internal ROM access is
performed, PSEN strobe signal will not be output from this pin.
ALE
OH
High
ADDRESS LATCH ENABLE: ALE enables the address latch that
separates the address from the data on Port 0.
RST
IL
-
RESET: Set this pin high for two machine cycles while the
oscillator is running to reset the device.
XTAL1
I
-
CRYSTAL 1: Crystal oscillator input or external clock input.
XTAL2
O
-
V_SS
I
-
V_DD
I
-
AVDD
I
-
CRYSTAL 2: Crystal oscillator output.
GROUND: Ground potential.
POWER SUPPLY: Supply voltage for operation.
Analog power supply.
AVSS
I
-
Analog ground potential.
I/O
P0.0−P0.7 _{D S H}
High-Z
PORT 0: Port 0 is an open-drain bi-directional I/O port. This port
also provides a multiplexed low byte address/data bus during
accesses to external memory. There is an embedded weakly pull-
up resistor on each port 0 pin which can be enabled or disabled by
setting or clearing of PUP0, bit0 in A2h. The ports have alternate
functions which are described below:
P0.0, AD0, MISO
P0.1, AD1, MOSI
P0.2, AD2, SPCLK
P0.3, AD3, /SS
P0.4, AD4, INT2
P0.5, AD5, INT3
P0.6, AD6, INT4
P0.7, AD7, INT5
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Publication Release Date: April 15, 2008
Revision A4.0