W79E225A Datasheet, PDF (92/200 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/227A Data Sheet
SOURCE
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
Timer 2 Overflow
A/D Converter
I2C Channel
Serial Port 1
SPI interrupt
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
PWM Period
PWM Brake
Timer 3 Overflow
Capture
Input/Direction
Interrupt/QEI
NVM Interrupt
Watchdog Timer
FLAG
VECTOR
ADDRESS
FLAG CLEARED BY
PRIORITY
LEVEL
IE0
0003H
Hardware, Follow the
inverse of pin
1(highest)
TF0
000BH
Hardware, software 2
IE1
0013H
Hardware, Follow the
inverse of pin
3
TF1
001BH
Hardware, software 4
RI + TI
0023H
Software
5
TF2 + EXF2
002BH
Software
6
ADCI
0033H
Software
7
I2C1 SI
003BH
Software
8
RI_1 + TI_1
007BH
Software
9
SPIF + MODF +
SPIOVF
0083H
Software
10
IE2
0043H
Hardware, software 11
IE3
004BH
Hardware, software 12
IE4
0053H
Hardware, software 13
IE5
005BH
Hardware, software 14
PWMF
0073H
Software
15
BKF
006BH
Software
16
TF3
008BH
Software
17
CPTF0/QEIF+
CPTF1/DIRF+ 0093H
Software
18
CPTF2
NVMF
009BH
Software
19
WDIF
0063H
Software
20
Table 11- 1: Priority structure of interrupts
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met, the hardware will
execute an internally generated LCALL instruction which will vector the process to the appropriate
interrupt vector address. The conditions for generating the LCALL are;
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being executed.
3. The current instruction does not involve a write to IE, EIE, EIE1, IP, EIP, EIP1, IPH, EIPH or EIP1H
registers and is not a RETI.
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Publication Release Date: December 14, 2007
Revision A2.0