W79E225A Datasheet, PDF (59/200 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/227A Data Sheet
The WDCON SFR is set to x0xx 0000b on an external reset. WTRF is set to a 1 on a Watchdog timer
reset, but to a 0 on power on resets. POR is set to 1 by a power-on reset. EWT is cleared to 0 on a
Power-on reset, reset pin reset, Watch Dog Timer reset and ISP reset.
All the bits in this SFR have unrestricted read access. The bits of POR, WDIF, EWT and RWT require
Timed Access (TA) procedure to write. The remaining bits have unrestricted write accesses. Please
refer TA register description.
PWMP COUNTER LOW BITS REGISTER
Bit:
7
6
5
4
3
2
1
0
PWMP.7 PWMP.6 PWMP.5 PWMP.4 PWMP.3 PWMP.2 PWMP.1 PWMP.0
Mnemonic: PWMPL
Address: D9h
BIT
NAME
FUNCTION
7~0 PWMP.7 ~PWMP.0 PWM Counter Low Bits Register.
PWM0 LOW BITS REGISTER
Bit:
7
6
5
4
3
2
1
0
PWM0.7 PWM0.6 PWM0.5 PWM0.4 PWM0.3 PWM0.2 PWM0.1 PWM0.0
Mnemonic: PWM0L
Address: DAh
BIT
NAME
FUNCTION
7~0 PWM0.7 ~PWM0.0 PWM 0 Low Bits Register.
NVM LOW BYTE ADDRESS
Bit:
7
6
5
4
3
2
1
0
NVMADDR NVMADDR NVMADDR NVMADDR NVMADDR NVMADDR NVMADDR NVMADDR
L.7
L.6
L.5
L.4
L.3
L.2
L.1
L.0
Mnemonic: NVMADDRL
Address: DBh
BIT
NAME
FUNCTION
7~0
NVMADDRL.7~
NVMADDRL.0
NVM low byte address.
PWM CONTROL REGISTER 1
Bit:
7
6
PWMRUN Load
Mnemonic: PWMCON1
5
4
3
PWMF CLRPWM PWM6I
2
PWM4I
1
0
PWM2I PWM0I
Address: DCh
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Publication Release Date: December 14, 2007
Revision A2.0