W79E225A Datasheet, PDF (167/200 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/227A Data Sheet
18.3.6 Programmable serial clock’s phase and polarity
The clock polarity CPOL control bit selects active high or active low SPCLK clock, and has no
significant effect on the transfer format. The clock phase CPHA control bit selects one of two different
transfer protocols by sampling data on odd numbered SPCLK edges or on even numbered SPCLK
edges. Thus, both these bits enable selection of four possible clock formats to be used by SPI system.
The clock phase and polarity should be identical for the master SPI device and the communicating
slave device.
When CPHA equals 0, the SS line must be negated and reasserted between each successive serial
byte. Also, if the slave writes data to the SPI data register (SPDR) while SS is low, a write collision
error results. When CPHA equals 1, the SS line can remain low between successive transfers. The
figures from
Figure 18-2 to
- 167 -
Publication Release Date: December 14, 2007
Revision A2.0