W79E225A Datasheet, PDF (125/200 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/227A Data Sheet
Figure 14-26: Smart Fault Detector timing diagram
The smart fault detector consists of 2 status bits; SFCST and SFCDIR. A SFCST show status of 8 bits
counter is active or in-active, while SFCDIR shows the counter’s counting direction. When SFCST = 0,
SFCDIR keeps its’ state.
The s/w can manually disable and clear the 8 bits counter, by clearing SFCEN to 0.
The following tables show the tabulate accumulated low level Brake time with various Fosc/x dividers
and compares value, at 40MHz and 20MHz.
FOSC/X
SCMP[1:0]
4
16
64
128
1/4
10,000,000
0.40us
1.60us
6.40us
12.80us
1/8
5,000,000
0.80us
3.20us
12.80us
25.60us
1/16
2,500,000
1.60us
6.40us
25.60us
51.20us
1/128
312,500
12.80us
51.20us
204.80us
409.60us
Table 14-5: Example the accumulated low level time at 40 MHz
FOSC/X
SCMP[1:0]
4
16
64
128
1/4
1/8
1/16
5,000,000
0.80us
3.20us
12.80us
25.60us
2,500,000
1.60us
6.40us
25.60us
51.20us
1,250,000
3.20us
12.80us
51.20us
102.40us
Table 14-6: Example the accumulated low level time at 20 MHz
1/128
156,250
25.60us
102.40us
409.60us
819.20us
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Publication Release Date: December 14, 2007
Revision A2.0