W79E225A Datasheet, PDF (168/200 Pages) Winbond – 8-bit Microcontroller

Preliminary W79E225A/227A Data Sheet
Figure 18-9 show the SPI transfer format, with different CPOL and CPHA. When CPHA = 0, data is
sample on the first edge of SPCLK and when CPHA = 1 data is sample on the second edge of the
SPCLK. Prior to changing CPOL setting, SPE must be disabled first.
18.3.7 Receive double buffered data register
This device is single buffered in the transmit direction and double buffered in the receive direction.
This means that new data for transmission cannot be written to the shifter until the previous transfer is
complete; however, received data is transferred into a parallel read data buffer so the shifter is free to
accept a second serial byte.
As long as the first byte is read out of the read data buffer before the next byte is ready to be
transferred, no overrun condition occurs. If overrun occur, SPIOVF is set. Second byte serial data
cannot be transferred successfully into the data register during overrun condition and the data register
will remains the value of the previous byte. The figure below shows the receive data timing waveform
when overrun occur.
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Publication Release Date: December 14, 2007
Revision A2.0