W79E825A Datasheet, PDF (68/127 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E825A/824A/823B/822B Data Sheet
Continued .
Source
Vector
Interrupt
Flag
address Enable Bits
Interrupt
Priority
Flag cleared ^Arbitration
by
Ranking
External
Interrupt 1
IE1 0013H
EX1 (IE.2)
Hardware,
IP0H.2, IP0.2 Follow the
7
inverse of pin
KBI Interrupt KBF 003BH EKB (EIE.1) IP1H.1, IP1.1 Software
8
Comparator 1
Interrupt
CMF1 0063H
EC1 (EIE.2) IP1H.2, IP1.2 Software
9
Timer 1 Interrupt TF1 001BH ET1 (IE.3)
IP0H.3, IP0.3
Hardware,
software
10
Comparator 2
Interrupt
CMF2 0043H
EC2 (EIE.3) IP1H.3, IP1.3 Software
11
Serial Port Tx
and Rx
TI & RI 0023H
ES (IE.4)
IP0H.4, IP0.4 Software
12
PWM Interrupt BKF 0073H
EPWM (EIE.5) IP1H.5, IP1.5 Software
13 (lowest)
Note: 1. The ADC Converter can wake up Power Down Mode when its clock source is from internal RC.
Table 12-3: Vector location for Interrupt sources and power down wakeup
Power
Down
Wakeup
Yes
Yes
Yes
No
Yes
No
No
12.3 Response Time
The response time for each interrupt source depends on several factors, such as the nature of the
interrupt and the instruction underway. In the case of external interrupts INT0 and INT1 , they are
sampled at C3 of every machine cycle and then their corresponding interrupt flags IEx will be set or
reset. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has
occurred. These flag values are polled only in the next machine cycle. If a request is active and all
three conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes
four machine cycles to be completed. Thus there is a minimum time of five machine cycles between
the interrupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the
instruction being executed, then an additional delay is introduced. The maximum response time (if no
other interrupt is in service) occurs if the W79E825 series are performing a write to IE, EIE, IP0, IP0H,
IP1 or IP1H and then executes a MUL or DIV instruction. From the time an interrupt source is
activated, the longest reaction time is 12 machine cycles. This includes 1 machine cycle to detect the
interrupt, 2 machine cycles to complete the IE, EIE, IP0, IP0H, IP1 or IP1H access, 5 machine cycles
to complete the MUL or DIV instruction and 4 machine cycles to complete the hardware LCALL to the
interrupt vector location.
Thus in a single-interrupt system the interrupt response time will always be more than 5 machine
cycles and not more than 12 machine cycles. The maximum latency of 12 machine cycles is 48 clock
cycles. Note that in the standard 8051 the maximum latency is 8 machine cycles which equals 96
machine cycles. This is a 50% reduction in terms of clock periods.
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