W79E825A Datasheet, PDF (67/127 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E825A/824A/823B/822B Data Sheet
12.2 Priority Level Structure
The W79E825 series uses a four priority level interrupt structure (highest, high, low and lowest) and
supports up to 13 interrupt sources. The interrupt sources can be individually set to either high or low
levels. Naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. However
there exists a pre-defined hierarchy amongst the interrupts themselves. This hierarchy comes into play
when the interrupt controller has to resolve simultaneous requests having the same priority level. This
hierarchy is defined as table below. This allows great flexibility in controlling and handling many
interrupt sources.
PRIORITY BITS
IPXH
IPX
INTERRUPT PRIORITY LEVEL
0
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest priority)
Table 12-2: Four-level interrupt priority
Each interrupt source can be individually programmed to one of four priority levels by setting or
clearing bits in the IP0, IP0H, IP1, and IP1H registers. An interrupt service routine in progress can be
interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The
highest priority interrupt service cannot be interrupted by any other interrupt source. So, if two
requests of different priority levels are received simultaneously, the request of higher priority level is
serviced.
If requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. This is called the arbitration ranking. Note that the arbitration
ranking is only used to resolve simultaneous requests of the same priority level.
As below Table summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits,
arbitration ranking, and whether each interrupt may wake up the CPU from Power Down mode.
SOURCE
External
Interrupt 0
Brownout
Detect
Watchdog
Timer
Timer 0
Interrupt
FLAG
IE0
VECTOR ^INTERRUPT
ADDRESS
ENABLE
BITS
0003H EX0 (IE0.0)
INTERRUPT
FLAG
PRIORITY ^{CLEARED BY}
ARBITRATI
ON
RANKING
Hardware,
IP0H.0, IP0.0 Follow the
1(highest)
inverse of pin
POWER
DOWN
WAKEUP
Yes
BOF 002BH EBO (IE.5) IP0H.5, IP0.5 Software
2
Yes
WDIF 0053H EWDI (EIE.4) IP1H.4, IP1.4 Software
3
No
TF0 000BH ET0 (IE.1)
IP0H.1, IP0.1
Hardware,
software
4
No
I2C Interrupt SI
0033H
ADC Converter ADCI 005BH
EI2 (EIE.0)
EAD (IE.6)
IP1H.0, IP1.0 Software
IP0H.6, IP0.6 Hardware
5
No
6
Yes⁽¹⁾
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Publication Release Date: February 21, 2008
Revision A9