W79E825A Datasheet, PDF (35/127 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E825A/824A/823B/822B Data Sheet
Continued
BIT NAME
5 STA
4 STO
3 SI
2 AA
1-
0-
FUNCTION
The START flag.
0: The STA bit is reset, no START condition or repeated START condition will be
generated.
1: The STA bit is set to enter a master mode. The I2C hardware checks the status of
I2C bus and generates a START condition if the bus is free. If bus is not free, then
I2C waits for a STOP condition and generates a START condition after a delay. If
STA is set while I2C is already in a master mode and one or more bytes are
transmitted or received, I2C transmits a repeated START condition. STA may be
set any time. STA may also be set when I2C interface is an addressed slave
mode.
The bit STO bit is set while I2C is in a master mode. A STOP condition is transmitted
to the I2C bus. When the STOP condition is detected on the bus, the I2C hardware
clears the STO flag. In a slave mode, the STO flag may be set to recover from a bus
error condition. In this case, no STOP condition is transmitted to the I2C bus.
However, the I2C hardware behaves as if a STOP condition has been received and it
switches to the not addressable slave receiver mode. The STO flag is automatically
cleared by hardware. If the STA and STO bits are both set, then a STOP condition is
transmitted to the I2C bus if I2C is in a master mode (in a slave mode, I2C generates
an internal STOP condition which is not transmitted). I2C then transmits a START
condition.
0: When the SI flag is reset, no serial interrupt is requested, and there is no stretching
on the serial clock on the SCL line.
1: When a new SIO state is present in the I2STATUS register, the SI flag is set by
hardware, and, if the EA and ES bits (in IE register) are both set, a serial interrupt
is requested when SI is set. The only state that does not cause SI to be set is state
F8H, which indicates that no relevant state information is available. When SI is set,
the low period of the serial clock on the SCL line is stretched, and the serial
transfer is suspended. A high level on the SCL line is unaffected by the serial
interrupt flag. SI must be cleared by software.
The Assert Acknowledge Flag
0: A not acknowledge (high level to SDA) will be returned during the acknowledge
clock pulse on SCL when: 1) A data has been received while SIO is in the master
receiver mode. 2) A data byte has been received while SIO is in the addressed
slave receiver mode.
1: An acknowledge (low level to SDA) will be returned during the acknowledge clock
pulse on the SCL line when: 1) The own slave address has been received. 2) A
data byte has been received while SIO is in the master receiver mode. 3) A data
byte has been received while SIO is in the addressed slave receiver mode. 4) The
General Call address has been received while the general call bit (GC) in I2ADDR
is set.
Reserved.
Reserved.
- 35 -
Publication Release Date: February 21, 2008
Revision A9