W79E825A Datasheet, PDF (25/127 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E825A/824A/823B/822B Data Sheet
BIT NAME
FUNCTION
7-0 DIVM.[7:0] The DIVM register is clock divider of uC. Refer OSCILLATOR chapter.
SERIAL PORT CONTROL
Bit: 7
6
5
4
3
2
1
0
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
Mnemonic: SCON
Address: 98h
BIT NAME
FUNCTION
Serial port mode select bit 0 or Framing Error Flag: The SMOD0 bit in PCON SFR
7
SM0/FE
determines whether this bit acts as SM0 or as FE. The operation of SM0 is
described below. When used as FE, this bit will be set to indicate an invalid stop
bit. This bit must be manually cleared in software to clear the FE condition.
6 SM1
Serial Port mode select bit 1. See table below.
5 SM2
Multiple processors communication. Setting this bit to 1 enables the multiprocessor
communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI
will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1,
then RI will not be activated if a valid stop bit was not received. In mode 0, the SM2
bit controls the serial port clock. If set to 0, then the serial port runs at a divide by
12 clock of the oscillator. This gives compatibility with the standard 8052. When set
to 1, the serial clock become divide by 4 of the oscillator clock. This results in faster
synchronous serial communication.
4 REN
Receive enable:
0: Disable serial reception.
1: Enable serial reception.
3 TB8
This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by
software as desired.
2 RB8
In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is the
stop bit that was received. In mode 0 it has no function.
1 TI
Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in
mode 0, or at the beginning of the stop bit in all other modes during serial
transmission. This bit must be cleared by software.
0 RI
Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in
mode 0, or halfway through the stop bits time in the other modes during serial
reception. However the restrictions of SM2 apply to this bit. This bit can be cleared
only by software.
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Publication Release Date: February 21, 2008
Revision A9