W79E825A Datasheet, PDF (101/127 Pages) Winbond – 8-BIT MICROCONTROLLER

W79E825A/824A/823B/822B Data Sheet
24 ANALOG-TO-DIGITAL CONVERTER
The ADC contains a DAC which converts the contents of a successive approximation register to a
voltage (VDAC) which is compared to the analog input voltage (Vin). The output of the comparator is
fed to the successive approximation control logic which controls the successive approximation
register. A conversion is initiated by setting ADCS in the ADCCON register. There are two triggering
methods by ADC to start conversion, either by purely software start or external pin STADC triggering.
The software start mode is used to trigger ADC conversion regardless of ADCCON.5 (ADCEX) bit is
set or cleared. A conversion will start simply by setting the ADCCON.3 (ADCS) bit. As for the
external STADC pin triggering mode, ADCCON.5 (ADCEX) bit has to be set and a rise edge pulse has
to apply to STADC pin to trigger the ADC conversion. For the rising edge triggering method, a
minimum of at least 2 machine cycles symmetrical pulse is required.
The low-to-high transition of STADC is recognized at the end of a machine cycle, and the conversion
commences at the beginning of the next cycle. When a conversion is initiated by software, the
conversion starts at the beginning of the machine cycle which follows the instruction that sets ADCS.
ADCS is actually implemented with tpw flip-flops: a command flip-flop which is affected by set
operations, and a status flag which is accessed during read operations.
The next two machine cycles are used to initiate the converter. At the end of the first cycle, the ADCS
status flag is set end a value of “1” will be returned if the ADCS flag is read while the conversion is in
progress. Sampling of the analog input commences at the end of the second cycle.
During the next eight machine cycles, the voltage at the previously selected pin of one of analog input
pin is sampled, and this input voltage should be stable in order to obtain a useful sample. In any event,
the input voltage slew rate must be less than 10V/ms in order to prevent an undefined result.
The successive approximation control logic first sets the most significant bit and clears all other bits in
the successive approximation register (10 0000 0000b). The output of the DAC (50% full scale) is
compared to the input voltage Vin. If the input voltage is greater than VDAC, then the bit remains set;
otherwise if is cleared.
The successive approximation control logic now sets the next most significant bit (11 0000 0000b or
01 0000 0000b, depending on the previous result), and the VDAC is compared to Vin again. If the
input voltage is greater then VDAC, then the bit remains set; otherwise it is cleared. This process is
repeated until all ten bits have been tested, at which stage the result of the conversion is held in the
successive approximation register. The conversion takes four machine cycles per bit.
The end of the 10-bit conversion is flagged by control bit ADCCON.4 (ADCI). The upper 8 bits of the
result are held in special function register ADCH, and the two remaining bits are held in ADCCON.7
(ADC.1) and ADCCON.6 (ADC.0). The user may ignore the two least significant bits in ADCCON and
use the ADC as an 8-bit converter (8 upper bits in ADCH). In any event, the total actual conversion
time is 52 machine cycles. ADCI will be set and the ADCS status flag will be reset 52 cycles after the
ADCS is set. Control bits ADCCON.0 and ADCCON.1 are used to control an analog multiplexer which
selects one of 4 analog channels. An ADC conversion in progress is unaffected by an external or
software ADC start. The result of a completed conversion remains unaffected provided ADCI = logic 1;
a new ADC conversion already in progress is aborted when the idle or power down mode is entered.
The result of a completed conversion (ADCI = logic 1) remains unaffected when entering the idle
mode.
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Publication Release Date: February 21, 2008
Revision A9