W981208BH Datasheet, PDF (6/41 Pages) Winbond – 4M x 4 BANKS x 8 BIT SDRAM

W981208BH
AC CHARACTERISTICS AND OPERATING CONDITION
(Vcc = 3.3V ± 0.3V, Ta = 0° to 70°C; Notes: 5, 6, 7, 8)
PARAMETER
SYM.
Ref/Active to Ref/Active Command
Period
Active to precharge Command
Period
Active to Read/Write Command
Delay Time
Read/Write(a) to
Read/Write(b)Command Period
Precharge to Active Command
Period
Active(a) to Active(b) Command
Period
Write Recovery Time
CL* = 2
CL* = 3
CLK Cycle Time
CL* = 2
CL* = 3
CLK High Level width
CLK Low Level width
Access Time from CLK
CL* = 2
CL* = 3
Output Data Hold Time
Output Data High Impedance Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK
(Rise and Fall)
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode register Set Cycle Time
*CL = CAS Latency
t_RC
t_RAS
t_RCD
t_CCD
t_RP
t_RRD
t_WR
t_CK
t_CH
t_CL
t_AC
t_OH
t_HZ
t_LZ
t_SB
t_T
t_DS
t_DH
t_AS
t_AH
t_CKS
t_CKH
t_CMS
t_CMH
t_REF
t_RSC
-7
(PC133, CL2)
MIN.
MAX.
57
-75
(PC133, CL3)
MIN.
MAX.
65
42 100000 45 100000
15
20
1
1
15
20
15
15
7.5
10
7
7.5
7.5
1000
10
1000
7
1000
7.5
1000
2.5
2.5
2.5
2.5
5.4
6
5.4
5.4
3
3
3
7
3
7.5
0
0
0
7
0
7.5
0.5
10
0.5
10
1.5
1.5
0.8
0.8
1.5
1.5
0.8
0.8
1.5
1.5
0.8
0.8
1.5
1.5
0.8
0.8
64
64
14
15
-8H
(PC100)
MIN.
MAX.
68
48 100000
20
1
20
20
10
8
10
1000
8
1000
3
3
6
6
3
3
8
0
0
8
0.5
10
2
1
2
1
2
1
2
1
64
16
UNIT
nS
Cycle
nS
mS
nS
-6-