W981208BH Datasheet, PDF (31/41 Pages) Winbond – 4M x 4 BANKS x 8 BIT SDRAM

Operating Timing Example, continued
Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
W981208BH
CLK
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS
RAS
CAS
WE
BS0
tRCD
BS1
A10
RBa
A0-A9,
A11
RBa
DQM
CKE
DQ
CBv
CBw
CBx CBy CBz
tAC
av0 av1 av2 av3
Q
Q
Q
Q
aw0
D
ax0 ay0
D
D
tAC
az0 az1 az2 az3
Q
Q
Q
Q
Bank #0 Active
Bank #1
Bank #2
Idle
Bank #3
Read
Single Write Read
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Publication Release Date: October 2000
Revision A1