W981208BH Datasheet, PDF (34/41 Pages) Winbond – 4M x 4 BANKS x 8 BIT SDRAM

Operating Timing Example, continued
Autoprecharge Timing (Write Cycle)
W981208BH
0
1
2
(1) CAS Latency=2
( a ) burst length = 1
Command Write
AP
tWR
tRP
DQ
D0
( b ) burst length = 2
Command Write
DQ
D0
AP
tWR
D1
( c ) burst length = 4
Command
Write
DQ
D0
( d ) burst length = 8
Command Write
D1
D2
3
4
Act
Act
tRP
AP
tWR
D3
DQ
D0
D1
D2
D3
D4
(2) CAS Latency=3
Write ( a ) burst length = 1
Command
AP
Act
tWR
tRP
DQ
D0
( b ) burst length = 2
Command Write
DQ
( c ) burst length = 4
Command
D0
Write
AP
tWR
D1
DQ
( d ) burst length = 8
D0
Command _Write
D1
D2
tRP
AP
tWR
D3
DQ
D0
D1
D2
D3
D4
5
6
Act
tRP
D5 D6
Act
tRP
D5 D6
7
8
AP
tWR
D7
Act
AP
tWR
D7
9
10 11
Act
tRP
Act
tRP
Note )
Write
represents the Write with Auto precharge command.
AP
represents the start of internal precharging.
Act
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS (min).
- 34 -