W981208BH Datasheet, PDF (29/41 Pages) Winbond – 4M x 4 BANKS x 8 BIT SDRAM

Operating Timing Example, continued
Auto Refresh Cycle
W981208BH
CLK
CS
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRP
tRC
tRC
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
CKE
DQ
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
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Publication Release Date: October 2000
Revision A1