W981208BH Datasheet, PDF (30/41 Pages) Winbond – 4M x 4 BANKS x 8 BIT SDRAM

Operating Timing Example, continued
Self Refresh Cycle
W981208BH
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12 13 14
15
16
17
18
19
20 21
22 23
CLK
CS
tRP
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
CKE
DQ
tSB
tCKS
tCKS
tCKS
Self Refresh Cycle
All Banks
Precharge
Self Refresh
Entry
tRC
No Operation Cycle
Arbitrary Cycle
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