W981208BH Datasheet, PDF (33/41 Pages) Winbond – 4M x 4 BANKS x 8 BIT SDRAM

Operating Timing Example, continued
Autoprecharge Timing (Read Cycle)
W981208BH
0
(1) CAS Latency=2
( a ) burst length = 1
Read ^Command
DQ
( b ) burst length = 2
Read ^Command
DQ
( c ) burst length = 4
Read ^Command
DQ
( d ) burst length = 8
Read ^Command
DQ
1
AP
(2) CAS Latency=3
( a ) burst length = 1
Read Command
AP
DQ
( b ) burst length = 2
Read Command
DQ
( c ) burst length = 4
Read Command
DQ
( d ) burst length = 8
Read Command
DQ
2
3
4
Act
tRP
Q0
AP
Act
tRP
Q0 Q1
AP
Q0 Q1 Q2
Q0 Q1 Q2
Act
tRP
Q0
AP
tRP
Q0 Q1
AP
Q0 Q1
Q0 Q1
5
6
7
Act
tRP
Q3
Q3 Q4 Q5
Act
Act
tRP
Q2 Q3
Q2 Q3 Q4
8
AP
Q6
AP
Q5
9
10
Act
tRP
Q7
tRP
Q6 Q7
11
Act
Note )
Read
AP
Act
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t RAS(min).
- 33 -
Publication Release Date: October 2000
Revision A1