W981208BH Datasheet, PDF (3/41 Pages) Winbond – 4M x 4 BANKS x 8 BIT SDRAM

W981208BH
PIN DESCRIPTION
PIN NO.
23 − 26, 22,
29 − 35
PIN
NAME
A0 − A11
FUNCTION
Address
20, 21
2, 5, 8, 11,
44, 47, 50,
53
19
BS0,
BS1
DQ0 −
DQ7
Bank Select
Data Input/
Output
CS
Chip Select
18
RAS
Row Address
Strobe
17
CAS
Column
Address
Strobe
16
WE
Write Enable
39
DQM Input/Output
Mask
38
CLK Clock Inputs
37
CKE Clock Enable
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
4, 7, 10, 13,
15, 36, 40,
42, 45, 48,
51
VCC
VSS
VCCQ
VSSQ
NC
Power (+3.3V)
Ground
Power (+3.3V)
for I/O buffer
Ground for I/O
Buffer
No Connection
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 − A11. Column address: A0 − A9.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock, RAS , CAS and WE define the operation
to be executed.
Referred to R A S
Referred to RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
with zero latency.
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode,
or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from VCC, to improve DQ noise
immunity.
Separated ground from VSS, to improve DQ noise
immunity.
No connection
Publication Release Date: October 2000
-3-
Revision A1